The present invention relates generally to the fabrication of integrated circuits and, more particularly, to a method for improved equivalent gate count yield estimation for integrated circuit devices.
The fabrication of integrated circuits is an extremely complex process that may involve hundreds of individual operations. Essentially, the process includes the diffusion of precisely predetermined amounts of dopant material into precisely predetermined areas of a silicon wafer to produce active devices such as transistors. This is typically done by forming a layer of silicon dioxide on the wafer, then utilizing a photomask and photoresist to define a pattern of areas into which diffusion is to occur through a silicon dioxide mask. Openings are then etched through the silicon dioxide layer to define the pattern of precisely sized and located openings through which diffusion will take place.
After a predetermined number of such diffusion operations have been carried out to produce the desired number of transistors in the wafer, they are interconnected as required by interconnection lines. These interconnection lines, or interconnects as they are also known, are typically formed by deposition of an electrically conductive material which is defined into the desired interconnect pattern by a photomask, photoresist and etching process. A typical completed integrated circuit may have millions of transistors contained within a 0.1 inch by 0.1 inch silicon chip and interconnects of submicron dimensions.
In view of the device and interconnect densities required in present day integrated circuits, it is imperative that the manufacturing processes be carried out with utmost precision and in a way that minimizes defects. For reliable operation, the electrical characteristics of the circuits must be kept within carefully controlled limits, which implies a high degree of control over the myriad of operations and fabrication processes. For example, in the photoresist and photomask operations, the presence of contaminants such as dust, minute scratches and other imperfections in the patterns on the photomasks can produce defective patterns on the semiconductor wafers, resulting in defective integrated circuits. Further, defects can be introduced in the circuits during the diffusion operations themselves. Defective circuits may be identified both by visual inspection under high magnification and by electrical tests. Once defective integrated circuits have been identified, it is desired to take steps to decrease the number of defective integrated circuits produced in the manufacturing process, thus increasing the yield of the integrated circuits meeting specifications.
In the present state of the art, accurate yield prediction for an integrated circuit design based on critical area analysis can be performed only after design of the integrated circuit design is complete, while relatively simple and inaccurate die size models are used to predict yield prior to the design being completed. As integrated circuits become increasingly more complex, it is found that the pre and post design yield predictions often do not agree. Financial considerations require a more accurate method for predicating yield (and thus cost) at the time a new integrated circuit is under consideration.
Logic library elements in current technologies have very different circuit packing density. In a conventional “equivalent gate count” modeling approach, it is assumed that all logic circuits are equally susceptible to defects. In practice, large differences are seen between different library elements. In addition, the presently used equivalent gate count prediction method assumes that circuits of a given type (e.g., logic circuits) are uniformly distributed over the entire surface of the die, when in fact this is not the case. Rather, many complex products contain areas of different circuit density. Thus, complex cores impact the yield of semiconductor parts that use these cores. Accordingly, there is a need for a further improved method for integrated circuit product yield prediction, as inaccurately predicted yields often result in poor business decisions when the product is quoted (e.g., lost business opportunity or lower than planned gross margin).